VISA 2026·MICRO 2026, Athens·Sat, Oct 31 · 13:00 – 17:00 EET
Call for papers
Short papers on the contract surface between AI agents, compilers, and rapidly evolving silicon.
4–6 pages · IEEE format
WIP · position · vision · early results
Due Sep 11, 2026 (AoE)
Submit a paper
// HotCRP link will appear here as soon as submissions open
visa.scope
Scope
VISA 2026 examines the virtual ISA — a stable, hardware-agnostic abstraction between high-level programming models and diverse hardware backends — as the pivotal interface of the agentic era: the contract surface where LLM-driven code synthesizers, autonomous autotuners, compilers, and microarchitectural innovation meet. When the programmer is a machine, the ISA must be self-describing enough to reason over and verifiable enough to trust.
We invite short papers (4–6 pages, IEEE format) describing work in progress, position papers, vision papers, or early results. The scope spans the full accelerator stack — ISA design and semantics, compilation and optimization, DSLs and programming models, hardware co-design, and deployment experience. The agent-facing interface is the flagship theme that runs through all of them: wherever your work sits, we encourage you to ask how the problem changes when the primary reader and writer of the ISA is a machine.
visa.topics
Topics of interest
visa.agents
Agent-facing virtual ISA interfacesflagship topic
As LLM-driven code synthesizers and autonomous autotuners become first-class producers of accelerator code, the virtual ISA increasingly serves as the contract surface between AI agents and silicon. This is the question VISA exists to ask — and a lens we encourage across every topic below.
Self-describing virtual ISAs that expose semantics, cost, and resource footprints to LLM reasoners · well-typed, verifiable contracts for reliable agent code generation and equivalence checking · LLM-guided lowering, kernel synthesis, and closed-loop autotuning through the virtual ISA layer · safety and sandboxing for agent-generated kernels · benchmarks for the agent-programmability of a virtual ISA · self-evolving virtual ISAs that let agents refine abstractions and lowering strategies through iterative feedback.
visa.design
Virtual ISA design & abstraction
Principles for defining stable virtual ISA boundaries · formal semantics, correctness, and versioning strategies · capability negotiation, feature discovery, and introspection mechanisms · effect systems, memory models, and concurrency semantics suited to heterogeneous architectures.
visa.codesign
Virtual ISA / (micro)architecture co-design & optimization
How can architects exploit a virtual ISA abstraction to deliver aggressive hardware optimizations while preserving programmability — echoing recent MICRO/HPCA/ISCA themes such as LLM serving, MoE and sparsity acceleration, dataflow fabrics, near-/in-memory compute, chiplet systems, and KV-cache-centric memory hierarchies?
Late binding of physical resources at virtual-to-physical lowering · cost-model-aware virtual ISAs that surface architectural knobs (parallelism, dataflow, precision, locality) without leaking microarchitectural detail · reconfigurable and spatial backends targeted from a common virtual ISA · co-designing virtual ISA primitives with emerging hardware features · dynamic-shape execution under stable semantics · quantitative studies of the programmability–performance Pareto frontier.
visa.compilers
Compiler optimizations
Lowering and legalization targeting virtual ISAs · optimization across the virtual-to-physical ISA boundary · polyhedral, tile-level, and search-based techniques · profile-guided compilation, equivalence checking, and differential testing at the virtual ISA level · LLM-aware compilation (kernel fusion, KV-cache-aware scheduling, MoE graph partitioning) · directive- and may-directive-based compilation guided by programming-model annotations that inform but do not over-constrain the optimizer.
visa.dsl
DSLs & programming models
DSL frontends (Triton-style tile languages, dataflow and graph DSLs, agentic pipeline languages) lowering to virtual ISAs · type systems for accelerator programming · auto-tuning and search-based code generation · abstractions for emerging AI workloads — LLM inference and training, MoE routing, long-context attention, KV-cache management, multi-modal and agentic serving pipelines · DSL-embedded profiling APIs that expose counters, traces, and hardware metrics as first-class language constructs for feedback-driven optimization.
visa.infra
Case studies & infrastructure
Real-world virtual ISA deployments (AI, HPC, networking, signal processing) · open-source frameworks and benchmarks · simulation, modeling, and HW/SW co-design flows enabled by virtual ISAs · production lessons from MLIR dialects, PTX, SPIR-V, StableHLO, TOSA, Triton-IR, CUDA Tile IR, Ascend PTO, and related stacks.
// topics include, but are not limited to, the above.